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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-454AD645
4M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE
Description
The MC-454AD645 is a 4,194,304 words by 64 bits synchronous dynamic RAM module on which 16 pieces of 16M SDRAM: PD4516821A are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 4,194,304 words by 64 bits organization * Clock frequency and clock access time
Family /CAS latency Clock frequency (MAX.) MC-454AD645F-A80 CL = 3 CL = 2 MC-454AD645F-A10 CL = 3 CL = 2 MC-454AD645F-A12 CL = 3 CL = 2 MC-454AD645FA-A10B CL = 3 CL = 2 125 MHz 83 MHz 100 MHz 77 MHz 83 MHz 67 MHz 100 MHz 77 MHz Clock access time (MAX.) 6 ns 7 ns 7 ns 8 ns 8 ns 9 ns 7 ns 8 ns Power consumption (MAX.) Active 5,414 mW 4,406 mW 4,550 mW 3,686 mW 3,974 mW 3,110 mW 3,686 mW 3,398 mW Standby 115.2 mW (CMOS level input)
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Dual internal banks controlled by BA0 (Bank Select) * Programmable burst-length: 1, 2, 4, 8 and full page * Programmable wrap sequence (sequential / interleave) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * All DQs have 10 10 % of series resistor * Single 3.3 V 0.3 V power supply * LVTTL compatible * 2,048 refresh cycles / 32 ms * Burst termination by Burst Stop command and Precharge command * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Unbuffered type * Serial PD
The information in this document is subject to change without notice.
Document No. M12666EJ5V0DS00 (5th edition) Date Published July 1998 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
1997
MC-454AD645
Ordering Information
Part number Clock frequency (MAX.) MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12 MC-454AD645FA-A10B 125 MHz 100 MHz 83 MHz 100 MHz 168-pin Dual In-line Memory Module (Socket Type) Edge connector : Gold plated 29.21 mm (1.15 inch) height 16 pieces of PD4516821AG5 (Rev. P) (400 mil TSOP (II)) [Double side] 16 pieces of PD4516821AG5 (400 mil TSOP (II)) [Double side] Package Mounted devices
2
MC-454AD645
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) [MC-454AD645F, MC-454AD645FA] /xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC VSS NC NC Vcc /CAS DQMB4 DQMB5 /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 (A11) NC Vcc CLK1 NC VSS CKE0 /CS3 DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 NC Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
A0 - A10 BA0 (A11) DQ0 - DQ63 CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 /RAS /CAS /WE SA0 - SA2 SDA SCL VCC VSS NC
: Address Inputs : SDRAM Bank Select : Data Inputs / Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : No Connection
[Row : A0 - A10, Column : A0 - A8]
DQMB0 - DQMB7 : DQ Mask Enable
3
MC-454AD645
Block Diagram
/WE /CS0 DQMB0 /CS1 /CS2 DQMB2 /CS3
DQ 3 DQ 2 DQ 1 DQ 0 DQ 7 DQ 6 DQ 5 DQ 4
DQMB1
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D0 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D8 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 19 DQ 18 DQ 17 DQ 16 DQ 23 DQ 22 DQ 21 DQ 20
DQMB3
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D2 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D10 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 11 DQ 10 DQ 9 DQ 8 DQ 15 DQ 14 DQ 13 DQ 12
DQMB4
DQ 0 DQM DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
/CS
/WE
D1
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D9 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 27 DQ 26 DQ 25 DQ 24 DQ 31 DQ 30 DQ 29 DQ 28
DQMB6
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D3 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D11 DQ 4 I/O 5 I/O 6 I/O 7
/WE
DQ 35 DQ 34 DQ 33 DQ 32 DQ 39 DQ 38 DQ 37 DQ 36
DQMB5
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D4 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D12 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 51 DQ 50 DQ 49 DQ 48 DQ 55 DQ 54 DQ 53 DQ 52
DQMB7
DQ 0DQM /CS DQ 1 DQ 2 DQ 3 D6 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D14 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 43 DQ 42 DQ 41 DQ 40 DQ 47 DQ 46 DQ 45 DQ 44
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D5 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D13 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 59 DQ 58 DQ 57 DQ 56 DQ 63 DQ 62 DQ 61 DQ 60
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D7 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D15 DQ 4 DQ 5 DQ 6 DQ 7
/WE
SERIAL PD SCL A0 A1 A2 SDA
CLK0
CLK : D0, D4 CLK : D1, D5
CLK : D2, D6 CLK2 CLK : D3, D7
CLK1 SA0 SA1 SA2
CLK : D8, D12 CLK : D9, D13
CLK3
CLK : D10, D14 CLK : D11, D15
A0 - A10 BA0 VCC C VSS
A0 - A10: D0 - D15 A11: D0 - D15 D0 - D15 D0 - D15
/RAS /CAS CKE0
/RAS: D0 - D15 /CAS: D0 - D15 CKE: D0 - D7 CKE1 10 k CKE : D8-D15
Remarks 1. The value of all resistors is 10 except CKE1. 2. D0 - D15 : PD4516821A (1M words x 8 bits x 2 banks)
4
MC-454AD645
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -1.0 to +4.6 -1.0 to +4.6 50 16 0 to +70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Symbol VCC VIH MC-454AD645F MC-454AD645FA Low level input voltage Operating ambient temperature VIL TA Condition MIN. 3.0 2.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 4.6 VCC+0.3 +0.8 70 V C Unit V V
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 Test condition A0 - A10, BA0 (A11), /RAS, /CAS, /WE CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 DQMB0 - DQMB7 DQ0 - DQ63 MC-454AD645F MC-454AD645FA MIN. TYP. MAX. 80 36 50 34 15 15 20 pF Unit pF
5
Data input / output capacitance
CI/O
5
MC-454AD645
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) [MC-454AD645F]
Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC (MIN.), IO = 0 mA Test condition /CAS latency = 2 Grade -A80 -A10 -A12 /CAS latency = 3 -A80 -A10 -A12 Precharge standby current in power down mode Precharge standby current in non power down mode ICC2NS ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. Active standby current in power down mode Active standby current in non power down mode ICC3NS ICC3P ICC3PS ICC3N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. Operating current (Burst mode) ICC4 tCK tCK (MIN.), IO = 0 mA /CAS latency = 2 -A80 -A10 -A12 /CAS latency = 3 -A80 -A10 -A12 Refresh current Self refresh current Input leakage current Input leakage current (CKE1) Output leakage current High level output voltage Low level output voltage IO (L) VOH VOL DOUT is disabled, VO = 0 to 3.6 V IO = -2.0 mA IO = +2.0 mA ICC5 ICC6 II (L) tRC = 100 ns, tCK = MIN. CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V -80 -500 -10 2.4 0.4 1,224 1,024 864 1,504 1,264 1,104 944 32 +80 +500 +10 mA mA 3 mA 2 160 48 32 448 mA mA 96 MIN. MAX. 1,024 944 944 1,064 984 984 48 32 400 mA mA Unit Notes mA 1
A
A
V V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
MC-454AD645
[MC-454AD645FA]
Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC (MIN.), IO = 0 mA Precharge standby current in power down mode Precharge standby current in non power down mode ICC2NS ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. Active standby current in power down mode Active standby current in non power down mode ICC3NS ICC3P ICC3PS ICC3N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. Operating current (Burst mode) Refresh current Self refresh current Input leakage current Input leakage current (CKE1) Output leakage current High level output voltage Low level output voltage IO (L) VOH VOL DOUT is disabled, VO = 0 to 3.6 V IO = -4.0 mA IO = +4.0 mA ICC5 ICC6 II (L) ICC4 tCK tCK (MIN.), IO = 0 mA tRC = 100 ns, tCK = MIN. CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V -16 -500 -3 2.4 0.4 /CAS latency = 2 -A10B /CAS latency = 3 -A10B 904 1,024 944 16 +16 +500 +3 mA mA 3 mA 2 192 48 32 448 mA mA 96 Test condition Grade /CAS latency = 2 -A10B /CAS latency = 3 -A10B MIN. MAX. 944 984 48 32 400 mA mA Unit Notes mA 1
A
A
V V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
7
MC-454AD645
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). * An access time is measured at 1.4 V.
tCK tCH CLK 2.0 V 1.4 V 0.8 V tSETUP tHOLD 2.0 V 1.4 V 0.8 V tAC tOH Output tCL
Input
8
MC-454AD645
Synchronous Characteristics [MC-454AD645F]
Parameter Symbol -A80 MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time /CAS latency = 3 /CAS latency = 2 Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time tCMH 1.0 1.0 1.5 ns tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 3 3 3 0 3 3 2.0 1.0 2.0 1.0 2.0 1.0 2.0 2.0 6 7 8 12 MAX.
(125 MHz) (83 MHz)
-A10 MIN. 10 13 MAX.
(100 MHz) (77 MHz)
-A12 MIN. 12 15 MAX.
(83 MHz) (67 MHz)
Unit
Note
ns ns ns ns ns ns ns ns 1 1 1
6 7 3.5 3.5 3 0 3 3 2.5 1.0 2.5 1.0 2.5 1.0 2.5 2.5
7 8 4 4 3 0 7 8 3 3 3.0 1.5 3.0 1.5 3.0 1.5 3.0 3.0
8 9
8 9
ns ns ns ns ns ns ns ns ns ns
Note 1. Output load
1.4 V Z = 50 Output 50 pF 50
Remark
These specifications are applied to the monolithic device.
9
MC-454AD645
[MC-454AD645FA]
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time /CAS latency = 3 /CAS latency = 2 Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time tCMH 1.0 ns tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 3.5 3.5 3 0 3 3 2.5 1.0 2.5 1.0 2.5 1.0 2.5 2.5 7 8 10 13 -A10B MAX. (100 MHz) (77 MHz) 7 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note
Note 1. Output load
1.4 V Z = 50 Output 50 pF 50
Remark
These specifications are applied to the monolithic device.
10
MC-454AD645
Asynchronous Characteristics [MC-454AD645F]
Parameter Symbol -A80 MIN. REF to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT (0) to ACT (1) command period Data-in to PRE command period Data-in to ACT (REF) command /CAS latency = 3 period (Auto precharge) /CAS latency = 2 Mode register set cycle time Transition time Refresh time tDAL2 tRSC tT tREF tRC tRAS tRP tRCD tRRD tDPL tDAL3 80 48 24 24 16 8 1CLK +24 1CLK +24 2 0.5 30 32
120,000
-A10 MIN. 90 60 26 26 20 10 1CLK +26 1CLK +26 2 1 30 32
120,000
-A12 MIN. 90 60 30 30 24 12 1CLK +30 1CLK +30 2 1 30 32
120,000
Unit
Note
MAX.
MAX.
MAX. ns ns ns ns ns ns ns ns CLK ns ms
11
MC-454AD645
[MC-454AD645FA]
Parameter Symbol MIN. REF to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT (0) to ACT (1) command period Data-in to PRE command period Data-in to ACT (REF) command /CAS latency = 3 period (Auto precharge) Mode register set cycle time Transition time Refresh time /CAS latency = 2 tRC tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 90 60 26 26 20 10 1CLK+26 1CLK+26 2 1 30 32 120,000 -A10B MAX. ns ns ns ns ns ns ns ns CLK ns ms Unit Note
12
MC-454AD645
Serial PD
[MC-454AD645F]
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 3 cycle time MC-454AD645F-A80
MC-454AD645F-A10 MC-454AD645F-A12
(1/2)
Hex 80H 08H 04H 0BH 09H 02H 40H 00H 01H 80H A0H C0H 60H 70H 80H 00H 80H 08H 00H 01H 8FH 02H 06H 01H 01H 00H 0EH C0H D0H F0H 70H 80H 90H 00H Bit 7 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 1 0 Bit 6 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 Bit 3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 Bit 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 Bit 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 12 ns 13 ns 15 ns 7 ns 8 ns 9 ns Notes 128 bytes 256 bytes SDRAM 11 rows 9 columns 2 banks 64 bits 0 LVTTL 8 ns 10 ns 12 ns 6 ns 7 ns 8 ns None Normal x8 None 1 clock 1, 2, 4, 8, F 2 banks 2, 3 0 0
10
CL = 3 access time MC-454AD645F-A80
MC-454AD645F-A10 MC-454AD645F-A12
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate / type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 cycle time MC-454AD645F-A80
MC-454AD645F-A10 MC-454AD645F-A12
24
CL = 2 access time MC-454AD645F-A80
MC-454AD645F-A10 MC-454AD645F-A12
25-26
13
MC-454AD645
(2/2)
Byte No. 27 tRP (MIN.) Function Described
MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12
Hex 18H 1AH 1EH 10H 14H 18H 18H 1AH 1EH 30H 3CH 3CH 04H 00H
Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Bit 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit 5 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1
Bit 4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0
Bit 3 1 1 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1
Bit 2 0 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0
Bit 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Notes 24 ns 26 ns 30 ns 16 ns 20 ns 24 ns 24 ns 26 ns 30 ns 48 ns 60 ns 60 ns 16M bytes
28
tRRD (MIN.)
MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12
29
tRCD (MIN.)
MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12
30
tRAS (MIN.)
MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12
31 32-61 62 63
Module bank density
SPD revision Checksum for bytes 0 - 62
MC-454AD645F-A80 MC-454AD645F-A10 MC-454AD645F-A12
01H 98H FCH 68H
64-71 72 73-90 91-92 93-94 95-98 99-125 126 127
Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Mfg specific Intel specification frequency Intel specification /CAS latency support 66H 06H 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 66 MHz 2, 3
14
MC-454AD645
[MC-454AD645FA]
Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-26 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 3 cycle time MC-454AD645FA-A10B CL = 3 access time MC-454AD645FA-A10B DIMM configuration type Refresh rate / type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 cycle time MC-454AD645FA-A10B CL = 2 access time MC-454AD645FA-A10B 04H 0BH 09H 02H 40H 00H 01H A0H 70H 00H 80H 08H 00H 01H 8FH 02H 06H 01H 01H 00H 0EH D0H 80H 00H 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 13 ns 8 ns SDRAM 11 rows 9 columns 2 banks 64 bits 0 LVTTL 10 ns 7 ns None Normal x8 None 1 clock 1, 2, 4, 8, F 2 banks 2, 3 0 0 08H 0 0 0 0 1 0 0 0 256 bytes Hex 80H Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
(1/2)
Notes 128 bytes
15
MC-454AD645
(2/2)
Byte No. 27 28 29 30 31 32-61 62 63 SPD revision Checksum for bytes 0 - 62 64-71 72 73-90 91-92 93-94 95-98 99-125 126 127 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Mfg specific Intel specification frequency Intel specification /CAS latency support 66H 06H 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 66 MHz 2, 3
MC-454AD645FA-A10B
Function Described tRP (MIN.) tRRD (MIN.) tRCD (MIN.) tRAS (MIN.)
MC-454AD645FA-A10B MC-454AD645FA-A10B MC-454AD645FA-A10B MC-454AD645FA-A10B
Hex 1AH 14H 1AH 3CH 04H 00H 01H FCH
Bit 7 0 0 0 0 0 0 0 1
Bit 6 0 0 0 0 0 0 0 1
Bit 5 0 0 0 1 0 0 0 1
Bit 4 1 1 1 1 0 0 0 1
Bit 3 1 0 1 1 0 0 0 1
Bit 2 0 1 0 1 1 0 0 1
Bit 1 1 0 1 0 0 0 0 0
Bit 0 0 0 0 0 0 0 1 0 1
Notes 26 ns 20 ns 26 ns 60 ns 16M bytes
Module bank density
Timing Chart Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
16
MC-454AD645
Package Drawing
[MC-454AD645F, MC-454AD645FA]
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
M1 (AREA B)
Y
Z
N
R Q M L
M2 (AREA A)
A
H K C G D
B
S
(OPTIONAL HOLES)
T U
J B I
E A1 (AREA A)
ITEM A A1 B C D D1 D2 E G H I J K L M M1 M2 N P Q R S T U V W X Y Z
MILLIMETERS 133.35 133.350.13 11.43 36.83 6.35 2.0 3.125 54.61 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 29.210.13 9.43 19.78 4.0 MAX. 1.0 R2.0 4.00.10
detail of A part W
detail of B part D2
V X
P D1
3.0
1.270.1 4.0 MIN. 0.25 MAX. 1.00.05 2.540.10 3.0 MIN. 3.0 MIN. M168S-50A65-1
17
MC-454AD645
[MEMO]
18
MC-454AD645
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. circuitry. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. initialized until the reset signal is received. Hence, power-on does not Reset operation must be guarantee out-pin levels, I/O settings or contents of registers. Device is not executed imme-diately after power-on for devices having reset function.
19
MC-454AD645
[MEMO]
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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